EC ENGR 201D · EE 201DDesign in Nanoscale Technologies
Electrical and Computer Engineering · 4 units · Graduate courses (200-299)
Challenges of digital circuit design and layout in deeply scaled technologies, with focus on design-manufacturing interactions. Summary of large-scale digital design flow; basic manufacturing flow; lithographic patterning, resolution enhancement, and mask preparation; yield and variation modeling; circuit reliability and aging issues; design rules and their origins; layout design for manufacturing; test structures and process control; circuit and architecture methods for variability mitigation.
Letter grading.
When it runs
- Spring 2026
Scheduled, not typical — from UCLA’s Schedule of Classes, which publishes Fall 2025 through Spring 2027 and nothing before it.
Requisites
Official UCLA wording
Enforced requisite: course 115C.
BruinTree reads · Prerequisite
confidence 1.00 · from textRequires
Everything that has to come before this course, not just the courses named in the requisite above.
EC ENGR 201D
- EC ENGR 115CDigital Electronic Circuits
- EC ENGR 100Electrical and Electronic Circuits
- PHYSICS 1CPhysics for Scientists and Engineers: Electrodynamics, Optics, and Special Relativity4 more beneath
- EC ENGR 115AAnalog Electronic Circuits I
- COM SCI M51ALogic Design of Digital Systems
1 direct requisite. Showing 9 courses over 3 levels; the branches marked with a count carry on past it. Every course here opens its own tree.
Unlocks
What this course is a requisite for, and what those courses lead to in turn.
No course in the catalog lists this as a requisite.